1. Field of the Invention
This invention relates to logic gate circuit designs in general and, more particularly, to energy efficient logic gate circuit designs, generally known as "adiabatic" logic or recovered energy logic.
2. Description of the Prior Art
Low energy computing requires the ability to implement complex logic functions with low power dissipation per gate even at high clock frequencies. Logic circuit designs that can provide energy efficient computation are available, such as that shown in U.S. patent applicant 08/069,994, filed May 28, 1993, having common inventors with this application and assigned to the same assignee. Further, the clock generator that drives the logic gate should be energy efficient such that the low energy advantage of the logic gate circuitry can be utilized. The low power logic and clock generators are sometimes referred to as "adiabatic" circuits since part of the energy used to perform the computations is recovered and reused for the next computation.
An efficient clock generator circuit is disclosed in U.S. patent application 08/229258, filed Apr. 18, 1994, by the same inventors as this application and assigned to the same assignee. For the desired high efficiency operation of the clock generator, the capacitive load on the outputs of the clock generator should be substantially invariant with respect to the logic inputs, intermediate and final results of the logic circuitry.
The logic circuit design in the above-referenced patent application suffers from providing a clock load that is dependent the computational results within each logic gate. Thus, using this logic circuit design with the above-referenced clock generator compromises the efficiency of the clock generator and may produce undesired distortions on the clock signal.
Thus, it is desirable to provide an energy efficient logic gate circuit design that provides a substantially invariant load to a clock generator regardless of the logic signals within the logic circuit.
Further, it is desirable to provide an energy efficient logic gate circuit design that does not cause significant clock signal distortion depending on the logic signals within the logic gate.